1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to an embedded dynamic random access memory (EDRAM) having a capacitor-under-bitline (CUB) structure and a method of manufacturing such an EDRAM.
2. Description of the Related Art
As semiconductor devices have become more highly integrated, a system on a chip (SOC) technology has become more widely employed in semiconductor fabricating processes. The SOC technology provides value added features to the semiconductor device by integrating elements having various functions in single chip, thus reducing the number of chips required and the assembly complexity and potentially improving the speed and reliability of the desired functionality.
The SOC version of an embedded memory logic (EML) device, for instance, will typically include at least a memory device and a logic device integrated on single chip. Such an EML device may be divided into a cell array region and a logic circuit region. Memory cells disposed on the cell array region may then be used to store information processed by the logic circuit or provide information to the logic circuit from which new information may be generated. A DRAM cell or a SRAM cell may be used as the memory cell of the EML device.
The EDRAM fabricating process includes a reciprocal logic structure and a high-integrated DRAM structure. When a stack type capacitor structure is employed in the EDRAM device, the capacitor may be configured as either a CUB structure that is formed prior to forming a bit line or a capacitor-over-bitline (COB) structure that a capacitor is formed in conjunction with the form a bit line.
An advantage of the COB structure is that the capacitor may be formed without significant regard for the processing margin associated with the subsequent formation of the bit line during fabrication of the highly integrated semiconductor device. A disadvantage of the COB structure is that the cost of semiconductor fabrication is increased by the additional photolithographic processes, typically eight to ten, that may be required to add a COB structure to a standard logic device fabrication process. On the other hand, the use of a CUB structure tends to limit the degree to which the integration of the semiconductor device may be increased. However, the additional cost associated with including a CUB structure in a standard logic device fabrication process is reduced relative to a COB structure because only three to five additional photolithography processes are typically required.
As a result, CUB structures have been more widely utilized in the production of EDRAM devices. Because the electrical characteristics of a MOS transistor may be significantly influenced by the thermal budget associated with subsequent processing during device fabrication, cell capacitors utilizing a metal/insulator/metal (MIM) structure may be included in EDRAM devices to reduce the thermal budget.
FIG. 1 is a cross sectional view illustrating a conventional EDRAM device having a CUB structure. Referring to FIG. 1, a field region 12 is formed using a field isolation process on a substrate 10 that is divided into a cell array region A and a core/peripheral circuit/logic region B.
A gate oxide layer (not shown), a gate electrode 14, a gate spacer 16 and impurity regions (not shown) such as source/drain regions are formed at the surface portions of the substrate 10. The gate electrode 14 typically includes polysilicon and the gate spacer 16 typically includes silicon oxide and/or silicon nitride.
To improve the operational speed of the EDRAM device, a metal silicide layer 18, such as cobalt silicide, nickel silicide or titanium silicide, may be formed on the gate electrode 14 and the substrate 10 through a silicidating reaction. To form the metal silicide layer 18 on desired portions of the gate electrode 14 and the substrate 10, a silicidation blocking layer (SBL) 19 is formed on the gate spacer 16 before the metal silicide layer 18 is formed. The SBL 19 includes a material, such as silicon oxynitride that is generally non-reactive with the metal being used to form the silicide.
A first insulating layer 20 is formed on the resultant structure. The first insulating layer 20 is then patterned and etched to form a storage node contact hole 22a, a bit line contact hole 22b and a dummy metal contact hole 22c. The impurity-doped regions of the cell array region A are exposed through the storage node contact holes 22a and the bit line contact hole 22b. The gate electrode 14 and an impurity-doped region of the core/peripheral circuit/logic region B are exposed through the dummy metal contact holes 22c. 
A first metal layer, such as a tungsten layer, is then formed on the first insulating layer 20 to a thickness sufficient to fill the contact holes 22a, 22b and 22c. The uppermost portion of the first metal layer is then removed to expose the surface of the first insulating layer 20, typically through a chemical mechanical polishing (CMP) process or an etch-back process to form contact studs 23a, 23b and 23c that will serve to reduce the depth of a subsequent metal contact and reduce the contact resistance between a lower electrode 28 of a capacitor and the source region of the cell array region A.
A second insulating layer 26, typically including silicon oxide, is then formed on the contact studs 23a, 23b and 23c and the exposed surface of the first insulating layer 20. A capacitor 33 having an MIM structure is formed on the second insulating layer 26. The capacitor 33 includes a lower electrode 28, an upper electrode 32 and a dielectric layer 30. The lower and upper electrodes 28 and 32 may include tungsten nitride or titanium nitride and the dielectric layer 30 may include tantalum oxide (Ta2O5) or BST-based oxide.
A third insulating layer 34, typically including silicon oxide, is then formed on the second insulating layer 26. The third insulating layer 34 is then patterned and etched using a photolithography process to form metal contact holes 36a, 36b and 36c. The metal contact holes expose the upper surfaces of the contact stud 23b in the bit line contact hole 22b, the contact stud 23c in the dummy metal contact hole 22c and the upper electrode 32.
A second metal layer, such as a tungsten layer, is then formed on the third insulating layer 34 to a thickness sufficient to fill the metal contact holes 36a, 36b and 36c with the second metal layer. The uppermost portion of the second metal layer may then be removed through a CMP or an etch-back process to expose the upper surface of the third insulating layer 34 and thereby form metal plugs 37a, 37b and 37c. 
A third metal layer is then formed on the third insulating layer 34 and the metal plugs 37a, 37b and 37c. The third metal layer is patterned and etched through a photolithography process to form a bit line 38a that contacts the metal plugs 37a, 37b and 37c and first metal wirings 38b and 38c. 
According to the conventional method for forming an EDRAM having the CUB structure as described above, in order to reduce connection failures between the metal wiring and the impurity regions, the metal contacts are electrically connected to the contact studs 23a, 23b and 23c. Accordingly, the depth of the metal contact hole 36c formed in the core/peripheral circuit/logic region B is substantially identical to a sum of the height of the capacitor 33, the thickness of the upper electrode 32 and the thickness of the third insulating layer 34 between the upper electrode 32 and the first metal wiring 38c. Further, as a result of the separate processes associated with forming the contact studs required in the conventional method, at least three additional lithography processes must be added to the standard logic process to form the EDRAM.